• Document: PCI Express* Board Design Guidelines
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PCI Express* Board Design Guidelines DRAFT Intel Corporation June 2003 DRAFT *Other names and brands may be claimed as the property of others. PCI Express* Board Design Guidelines, DRAFT http://www.express-lane.org THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel, the Intel logo, and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the Untied States and other countries. § Other names and brands may be claimed as the property of others. Copyright  2003, Intel Corporation. All rights reserved. This document is accessible on the Web at: http://www.express-lane.org The PCI Express Base Specification and PCI Express Electromechanical Specification can be found on PCI-SIG web site: http://www.pcisig.com ii *Other names and brands may be claimed as the property of others. PCI Express* Board Design Guide, DRAFT http://www.express-lane.org Contents 1. Physical Interconnect Layout Design ................................................ 5 1.1 Introduction ........................................................................................................ 5 1.2 Topology and Interconnect Overview .............................................................. 5 1.2.1 Card Interoperability ............................................................................................... 7 1.2.2 Bowtie Topology Considerations ............................................................................ 7 1.2.2.1 Lane Polarity Inversion.................................................................................................... 8 1.2.2.2 Lane Reversal and Width Negotiation ............................................................................. 8 1.3 Physical Layout Design Constraints............................................................... 11 1.3.1 PCB Stackup.......................................................................................................... 11 1.3.1.1 Desktop System Board and Add-in Card (4-layer) Stackup .......................................... 12 1.3.1.2 Server, Workstation and Mobile (6-layer, 8-layer and 10-layer) Stackups.................... 15 1.3.1.3 Add-in Card and Mobile (6-layer) Stackup ................................................................... 16 1.3.2 PCB Trace and Other Element Considerations ..................................................... 17 1.3.2.1 Differential Pair Width and Spacing Impacts ................................................................ 20 1.3.2.2 Differential Pair Length Restrictions and Budgets ........................................................ 23 1.3.2.3 Length Matching............................................................................................................ 24 1.3.2.4 Reference Planes............................................................................................................ 25 1.3.2.5 Breakout Area Specific Routing Guidelines .................................................................. 27 1.3.2.6 Edge Finger Design: Add-in Card ................................................................................. 29 1.3.2.7 Via Usage and Placement .............................................................................................. 30 1.3.2.8 Bends ............................................................................................................................. 32 1.3.2.9 Test Points and Probing ................................................................................................. 35 1.3.3 PCI Express Topologies ........................................................................................ 35 1.3.3.1 Interconnect Topologies for Two Components on the Baseboard ................................. 36 1.3.3.2 Interconnect Topologies for Baseboard with Add-in

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