• Document: High-speed ADC Input Clock Issues
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High-speed ADC Input Clock Issues Application Note 1. Introduction The e2v converters family addresses the high-speed market in the field of ADCs as well as DACs, with frequencies operat- ing in the GHz range. Such high-speed devices require high-speed clock signals, which are usually subject to noise and which users are not used to deal with. As a matter of fact, the clock signal integrity is one of the main factor to be taken into account for proper operation of an ADC. High-speed ADCs require a low phase noise clock (namely a low jitter clock) in order to limit the dynamic performance deg- radation caused by noise on the clock. Even though many manufacturers offer crystal oscillators with the right jitter characteristics, only a few are able to generate clocks in the GHz range. These two issues are addressed in this paper, which intends to help the user understand the jitter phenomenon and design a proper clock with the right performance. 2. Input Clock Performance e2v Broadband Data Conversion products are high-speed products operating in the GHz range. They consequently require very high-speed signal management, which refers to two main parameters: • The signal integrity, involving the phase noise • The signal frequency itself The phase noise or jitter is defined in the next section, where the stress is laid on what jitter is, what it is due to and finally what impact it has on an A to D converter dynamic performances. A second half of this paragraph is dedicated to the comparison between differential and single-ended signaling used for high-speed signals. 2.1 Clock Jitter 2.1.1 What is Clock Jitter? We usually define the clock jitter for the case of an ADC, as the sample to sample variation in aperture delay of the clock signal. It is the uncertainty we have on the instant of sampling, which causes voltage errors at the sampling point. This is clearly illustrated in the following figure: Visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors SAS 2007 5433A–BDC–06/07 High-speed ADC Input Clock Issues Figure 2-1. Effect of Clock Jitter on the Instant of Sampling Analog Input Clock Different Codes Jitter Possible Clock Edge Positions ∆t As illustrated previously, jitter can be expressed in absolute time. In this case, what is stressed is the magnitude of the jitter and it is usually given in picoseconds, which is the appropriate order of magnitude for jitter. It might also be expressed in degrees, where one cycle of clock corresponds to 360°, but the normalized definition of jitter is in unit intervals, where one single unit interval corresponds to a clock period. This lat- ter definition gives the jitter as a fraction of one clock period. In our case, we usually give the jitter in absolute time. Finally, before getting into the causes of jitter, it can be highlighted that three types of jitter can be observed: • Regular and periodic jitter • Random jitter • Signal-dependent jitter Each type of jitter has a different cause and this will be developed in the following section. 2 5433A–BDC–06/07 e2v semiconductors SAS 2007 High-speed ADC Input Clock Issues 2.1.2 What Causes Jitter? Jitter can be defined as a time-based error and as such, is explained as the result of varying time delays in the signal path and waveform distortion due to poor impedance matching in the signal path. More technically speaking, the notion of jitter is connected to the phase noise, due to Frequency Modulation (FM), Amplitude Modulation (AM) and Phase Modulation (PM). However, the phase noise is not the only cause of jitter. As a matter of fact, thermal noise and spurious components have a non-negligible contribution to jit

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